1. Field of the Invention
This invention discloses a novel digital computer architecture designed to process large blocks of data wherein the same operation or sequence of operations is performed on all of the elements which make up the data block.
2. Description of the Prior Art
Conventional, general-purpose computer systems typically include a memory, central processing unit (CPU) and one or more input-output (I/O) channels with a plurality of peripheral devices. The central element in all data-processing transactions is the memory. The CPU communicates to and from the memory. Each peripheral device communicates via its I/O channel to the memory. For example, to transfer the contents of a magnetic tape record to an array processor in order to perform certain arithmetic operations on the data, the record from the magnetic tape must be transferred to the computer memory and thence from the computer memory to the array processor. That single transaction requires two data transfers. The first transfer results in a write to the computer memory from tape; the second transfer results in a read from memory to the array processor. In essence, the computer data-transfer bandwidth has been cut in half because of the two transfers required by a single transaction.
Typically, peripheral devices such as a magnetic tape drive, transfer data at a constant rate. The I/O channel to which a device is connected and the memory to or from which data are being transferred must be prepared to transmit or receive data at the rate required by the device, otherwise, an overrun condition will occur. Devices exhibiting that characteristic are defined as "I/O Synchronous" devices. On the other hand, a random access bulk storage memory that can tolerate a variable I/O transfer rate (not to exceed its maximum cycle time of course) may be classified as an "I/O asynchronous" device.
In conventional computer systems, the reason for routing all transactions through the computer memory is that typically both the source and receiver peripheral devices involved in a transaction, are of the I/O synchronous type. The computer memory acts as a buffer between the source and receiver peripheral devices.
In the example given earlier, the array processor is a device which has its own memory and it therefore behaves as an I/O asynchronous peripheral device. Theoretically, as far as synchronization of data transfer rates is concerned, data could be transferred directly from the magnetic tape drive to the array processor. In practice, known conventional computer architecture do not allow direct device-to-device transfers.
In signal processing in general and in seismic data processing in particular, large blocks of data are processed wherein the same operation is performed on all of the data elements that make up the data block. Therefore, only a relatively small amount of logic and control is required for a given block of computation that is to be performed on each of a very large number of data values. By contrast, business data processing, for which most general purpose computers are designed, requires relatively large amounts of logic and decision making for relatively small amounts of computation.
It is an object of this invention to provide a data processing system having novel architecture that will allow direct device-to-device data transfers without first detouring the data through memory.